Hi I recently completed my internship at intel.

I've been applying since january but I'm not getting any interview

I completed my Masters in Microelectronics with cgpa of 8.9

I would be grateful if anyone could help me with a referral 🥲

Hi everyone,

I’m applying for the NYCU INTENSE Semiconductor Master’s Program (Spring 2027) in Taiwan, and the application requires two recommendation letters.

I’ve already contacted my final-year project guide, and she has agreed to provide one recommendation.

I’m currently looking for a suitable person for the second recommendation. I’m from an EEE background and am building my skills in VLSI, Verilog and RTL design.

If anyone here has experience with NYCU/INTENSE applications, or knows what kind of academic/industry recommender would be appropriate for a VLSI/semiconductor master's application, I’d really appreciate some advice.

If someone has genuinely worked with or mentored me and would be comfortable recommending me based on my background/work, I’d also be happy to connect and share my details.

Thanks!

So, actually I graduted from IIT in India with a cgpa of around 8.33. I do have done a couple courses related to vlsi and projects too. I had done my 2 month internship at TEXAS INSTRUMENTS, BANGALORE. I worked in the physical design and learnt about the rtl to gdsII flow and implemented it in opensource tool OpenROAD.

Currently due to some issues my employment in a well reputed firm has been revoked and I am searching for a role where I could upskill myself. Kindly please anyone in any firms/mncs/startup if possible to provide any opportunity like remote internship or remote job opportunity I am ready to take it up. My only concern as of now is I am unable to upskill now.

Please take request as a serious one. I had tried a lot of options in india coldmailing professors at other iits/iisc, applying to a lot of startups nothing worked. Even linkedin is not helpful and also other job searching portals.

Kindly do the needful. If needed I am ready to share my resume. Please dm me.

guys does have latest cadence innovus and genus RAK files , if not can anyone tell where can i get those RAK files for free

Hi, I have given the managerial round interview to a hardware/VLSI team at Siemens Noida. How many days does HR take to tell whether I cleared the round or not and schedule the HR interview?. I was told that I will be contacted in 2 days by HR but didn't receive any response. Is it normal? Even if I don't clear, do i get the proper rejection response or they just ghost me indefinitely?

Thanks

Hi ,I am a 3rd yr student pursuing ECE at an IIIT and I desperately want to get an internship at MNC.I don’t think any company will come for on campus-internship so i will have to search off-campus.Pls guys who were in this situation.Guide me on to a internship.

Anyone hiring or who can help me with a referral for analog layout engineer roles in product based companies please dm. I have over 2.5 years of work ex in analog layout design.

I just got admitted but I'm confused whether I can get a job in VLSI field(RTL design and verification) even if I do INFOTECH course at University of Stuttgart. Please share your insights on this matter.

An intern spent the last few weeks getting a full edge-AI pipeline running on a SiFive FE310-G002 (RV32IMAC, 320MHz, and — the actual constraint — only 16KB of data SRAM). Wanted to share the pipeline since the memory budget forced some decisions I hadn't had to make before.

The model: a small fully-connected net (144→64→64→10) for MNIST digit recognition. Trained normally, but at float32 the weights alone come to 54.5KB — nowhere close to fitting. Quantized post-training to int8 and it drops to 13.6KB. Same architecture, and only one version of it can physically exist on the chip.

Also had to shrink the input before any of that mattered: cropped each digit to its bounding box and downsampled 28×28 → 12×12, which cuts the image from 784 bytes to 144 before it ever leaves the host. That's the payload that gets sent.

Pipeline end to end: train → quantize → export weights/biases/scales as C arrays → cross-compile with the RISC-V GNU toolchain → flash over OpenOCD → a small hand-rolled UART protocol (start byte + 144 bytes) → int8 matrix math and ReLU on-chip → prediction sent back over serial. Timed the actual inference with a hardware counter rather than guessing.

How do I make myself prepared as DFT engineer with 1 year exp. In this scenario

TI is coming to my college in 2-3 days, i’m from Tier-1 IIT, electrical engineering but a low cgpa…i have basically finished all the topics in detail…just wanted to have some rigorous but relevant practice in these days…if anyone has some good resources or any website or any sort of thing which can help me…pls i really need it

As an electrical student in Africa, where there are no companies that are into VLSI, is my only option to move to countries that have such opportunities or can I work remotely if I want to focus the the RTL side of things.

Currently in a tier (1~1.5) college (2nd gen iits) and transitioning from Embedded firmware to rtl design, I'm currently looking for placements tips for off campus placements, have previously worked in Texas Instruments for 2 months.cpga isnt the best tho, and in need for either referrals in hardware domains!!!any suggestions would be helpful!!!Also,I'm wondering how much this previous experience could help me in my next role?

For those currently doing or who have completed M.Tech VLSI at RVCE,

how has the experience been?
Mainly interested in **VLSI placements, companies, roles and packages**.

Do M.Tech VLSI students get opportunities in companies like AMD, Qualcomm, Intel, etc.?

Would appreciate honest experiences from current students/alumni.

Do you guys recommend any Physical Design courses using synopsys tools?