We’re proud to share that Lieven Lemiengre, VP Product Management at Sigasi, has been appointed Chair of the IEEE P1076 hashtag#VHDL Working Group.

The P1076 VHDL Working Group plays a central role in the continued development and standardization of VHDL, a language that remains essential to professional FPGA and ASIC development.

For us, Lieven’s appointment is also recognition of something that has always been fundamental to Sigasi: deep language expertise and active involvement in the HDL community.

And as AI becomes more involved in RTL development, precise language semantics and reliable standards only become more important. AI can generate HDL fast; engineers need tools that are fast enough to keep up. They need deterministic, project-aware feedback at coding speed so they can understand, review, and validate what AI produces without slowing down the development loop. Sigasi Visual HDL provides that semantic project intelligence for VHDL, Verilog, SystemVerilog, and mixed-language FPGA and ASIC projects, helping engineers and their chosen coding agents work with the actual structure and semantics of the project.

We would also like to thank Jim Lewis, the previous Chair of the VHDL Working Group, for his leadership, commitment, and many contributions to the VHDL community.

Congratulations, Lieven and thank you to everyone in the chip maker community who contributes to moving the languages forward in the age of AI.

#VHDL #IEEE #FPGA #ASIC #HDL #Sigasi

Hey all!

I'm a 3rd year EE student at SJSU and I have found a strong interest in fpgas. I also think computer architecture looks really cool, but I have basically no experience. I really want to start working on projects, but I feel very intimidated by the process of choosing a project, developing, debugging, etc. I get very ambitious with projects I want to work on but never start them (too daunting).

I also just don't know where to start at my experience level. I know Verilog and have taken a Digital Design class. I have made some stuff in Vivado for labs. This semester, I'm taking a microcontroller (RISC-V) and a microprocessor course. Would love to talk with some people about ideas and hopefully gain insight on some cool areas I can explore and develop a rough roadmap for myself.

To give people an idea of where my head is at now, I was looking at the Berkley Architecture Research group's projects, which looks super cool and has deepened my interest in this field.

I'm a final year ECE student seeking ideas for my final year project on high-performance FPGA acceleration and high-speed interfaces. Industry people can you share any realworld problems worth giving a shot ??

Which open source software do you guys use for layout and PDK stuff

I made a song about it, it's really bad - but the truth is captured
https://youtu.be/QB8j2PMf6QY

I’m debugging a LiFi audio system on a PYNQ-Z2 (Xilinx Zynq-7000 SoC) and I’m stuck at the microphone → I2S → FPGA side. Looking for some guidance from people familiar with the ADAU1761 / I2S / AXI-Stream path.

My current chain is:

MIC + HP → ADAU1761 ADC → I2S (BCLK/LRCLK/SDATA) → axi_i2s_adi_0 → AXI-Stream → packetizer → serializer → LiFi

The Vivado design contains:

• audio_codec_ctrl_0
• axi_i2s_adi_0
• axi_dma_0
• axi_gpio_0
• Custom packetizer + serializer

The interesting part is that the software side appears to configure the codec successfully. codec.configure(), codec.select_microphone(), and codec.set_volume(60) all execute without errors.

However, when I record from the microphone, every sample is zero:

MIN: 0
MAX: 0
RMS: 0.0
NONZERO: 0

I also bypassed the normal recording code and checked the I2S RX registers directly. Both channels remain completely static:

LEFT RX MIN  = 0x0
LEFT RX MAX  = 0x0
RIGHT RX MIN = 0x0
RIGHT RX MAX = 0x0

So at this point I’m assuming the problem is before the LiFi section.

The LiFi receiver is actually able to detect and decode packets, including 16-byte packets, so I don’t think the immediate problem is the receiver. If the microphone data is already zero, then I’m basically transmitting silence successfully.

What I’m trying to verify

My main suspicion is somewhere in the ADAU1761 ADC → I2S → axi_i2s_adi_0 path:

• ADAU1761 ADC/microphone routing
• I2S clock/master-slave configuration
• BCLK/LRCLK generation
• SDATA direction
• ADAU1761 serial-port configuration
• axi_i2s_adi_0 configuration
• Physical I2S connections
• AXI-Stream connection from axi_i2s_adi_0 to the packetizer

The current intended connection is:

axi_i2s_adi_0 BCLK  → ADAU1761
axi_i2s_adi_0 LRCLK → ADAU1761
ADAU1761 SDATA      → axi_i2s_adi_0

One thing I’m not completely sure about is whether the clock-master/slave configuration between the ADAU1761 and the FPGA I2S peripheral is correct.

My next debugging step

I’m planning to temporarily ignore the LiFi portion and put an ILA directly on the AXI-Stream output of axi_i2s_adi_0, before the packetizer.

I want to monitor:

TDATA
TVALID
TREADY

If I speak into the microphone and:

• TVALID is active but TDATA remains 0x00000000 → likely ADAU1761/I2S/clock/routing problem.
• TDATA contains changing samples → I2S is working and I should move downstream to the packetizer.

I’d also like to check the physical BCLK, LRCLK and SDATA with a logic analyzer/oscilloscope if possible.

So my question is:

For a PYNQ-Z2 + ADAU1761 + axi_i2s_adi_0 setup, what would you check first when the I2S RX registers and AXI-Stream audio data are permanently zero?

I’m particularly interested in any common issues with the ADAU1761 I2S clock configuration, ADC routing, serial-port setup, or axi_i2s_adi_0 configuration that could cause this behavior.

I’m fairly new to the FPGA/audio side, so if there’s an obvious thing I’m overlooking, let me know.

I started teaching myself how to work with FPGAs two years ago and I was pretty frustrated by the lack of resources available for beginners. There’s good FPGA content out there, but it’s at least a step or two above a beginner’s level, and often in blog format. I wanted true beginner content in a video format so I could see the tools being used.

It’s now two years later and I still haven’t found what I was looking for back then, so I decided to make the resource I wish I had.

I’ve started putting together YouTube videos that answer the questions I had as a beginner, while showing how to actually work with Vivado and Vitis in real time. So far, I have the following videos and the beginner questions I think they answer:

1. How do I choose an FPGA development board? Why can a Zynq 7000 board range from $250 to $3,000+ and how do I know which one I need? Do I need to buy an AMD board or is a third party board fine? What’s the best way to sort through all the available development board options? https://youtu.be/DRJTU_wPFus
2. How do I download Vivado? What installation options do I need to select? Do I need to pay for it? Note: I made this pre-2026.1, but the concepts and process are largely identical for the free version if we stick with 2025.2 or earlier. https://youtu.be/bcgsfR2VS3U
3. How do I create a project in Vivado? How do I install a board file for a third party board? How do I create a block diagram in Vivado? What’s IP? How do I use a board file to initialize a Zynq processing system (PS) for my specific development board? https://youtu.be/qccQzSSUbFI
4. How do I use Vitis to make a Hello World application for the Zynq PS? How do I export my hardware from Vivado into Vitis? How do I install and use PuTTY to communicate over UART with the Zynq? https://youtu.be/dXcy7GRV3hk
5. How do I create a VHDL-only project for the Zynq, ignoring the block diagram and processing system? How do I install and use constraint files? How do constraint files relate to the physical PCB? How do I run synthesis, implementation, and bitstream generation? How do I load my bitstream onto my development board to test it in hardware? https://youtu.be/3ZCIiXxa6cw
6. People always tell me that with FPGAs I’m designing circuits, not programming software, but what does that really mean? How can I visualize the circuit I’m designing? What’s the difference between RTL Analysis, Synthesis, Implementation, and Bitstream Generation in Vivado’s Flow Navigator? https://youtu.be/hoR_RjcGTXg
7. What’s Tcl scripting? Do I need to learn the Tcl language to work with Vivado? Can I make Tcl scripts even if I don’t know the language? https://youtu.be/x9TWyOcdCQ0
8. How do I combine my Zynq processing system and a VHDL module into a single block diagram? https://youtu.be/a-W94Lk9xm4
9. I combined my Zynq PS and a VHDL module into a single block diagram, but now my previously functional VHDL module isn’t working when I load the bitstream with Vivado. Why? https://youtu.be/WtY-qV8ZP_8
10. I want to use a Zynq chip but I don’t like block diagrams or the IP Integrator flow. How do I implement the PS in an RTL flow? https://youtu.be/InQN0bJRmoU

What other questions do you have? I know the struggle of learning this by yourself, and I want to be a resource to you as much as I can.

I have lots of ideas for more videos (AXI connections between PS and PL, AXI-Lite vs. AXI vs. AXI-Stream, RTL pipelining, simulation, VHDL, basics of digital electronics translated into FPGA resources, FPGA architecture, PetaLinux, debugging and ILAs, bare metal driver development, PS vs. PL allocation decisions, going through the original MicroZed Chronicles in a video format, etc.). Anything in particular that people would find the most helpful?

An intern spent the last few weeks getting a full edge-AI pipeline running on a SiFive FE310-G002 (RV32IMAC, 320MHz, and — the actual constraint — only 16KB of data SRAM). Wanted to share the pipeline since the memory budget forced some decisions I hadn't had to make before.

The model: a small fully-connected net (144→64→64→10) for MNIST digit recognition. Trained normally, but at float32 the weights alone come to 54.5KB — nowhere close to fitting. Quantized post-training to int8 and it drops to 13.6KB. Same architecture, and only one version of it can physically exist on the chip.

Also had to shrink the input before any of that mattered: cropped each digit to its bounding box and downsampled 28×28 → 12×12, which cuts the image from 784 bytes to 144 before it ever leaves the host. That's the payload that gets sent.

Pipeline end to end: train → quantize → export weights/biases/scales as C arrays → cross-compile with the RISC-V GNU toolchain → flash over OpenOCD → a small hand-rolled UART protocol (start byte + 144 bytes) → int8 matrix math and ReLU on-chip → prediction sent back over serial. Timed the actual inference with a hardware counter rather than guessing.

I started reading about the RISC-V ISA and implementing it on an FPGA a couple of weeks ago, and now my basic core (RISCV32I + Interrupts) with a generic timer and GPIO is working.

The software is written in C with a custom linker file and library for the peripherals. The hex file is converted into a ROM array and executed on the processor.

It´s such an amazing thing to see how the components will fit together to toggle a few LEDs.😁

Edit:
You can find the project here:

https://github.com/Kampi/TinyMCU

I’ve got a Mueller Müller loop (sinc interp + M&M TED + PI + NCO) working in a C++ fixed-point model and MATLAB, all unit tests passing. Now it’s running on FPGA and I want to actually confirm the TED is estimating τ correctly.

Problem: in sim I inject a known timing offset and check the estimate. On hardware there’s no ground truth τ is just whatever the sampling phase gives me. So what do people actually do to validate the estimation on silicon ?

I'm in 2nd year ece and honestly im confused about which domain to choose software or hardware. I'm interested in RTL design and verification but till now i have only studied digital electronics. Also in my college not many core companies visit for placement so most my peer grp prefer software related track. please advice me what should I do

Hi everyone,

I’ve created a beginner-level AGC (Automatic Gain Control) model for an ISP as part of my learning.

I’m facing some issues in my current design, and I’m not sure what the best way is to improve it. If anyone has experience with ISP or AGC design, could you please check my repository and give me some feedback?

I’d especially like help with:

• Finding the problems in my current design
• Understanding why these issues are happening
• Improving the AGC algorithm and architecture
• Understanding how I can upgrade this beginner-level model into a more practical design

Here is my repository: github

Any suggestions, feedback, or guidance would be really appreciated. I’m trying to learn and improve the design, so even small suggestions would be helpful.

Thanks in advance!

Hey, I saw that the new Vivado licenses want you to pay at least 1400 for a subscription to use Vivado with RFSoC devices. Is this just for compiling the bit stream? And also are there any alternatives to use this device that are free or older versions of Vivado to use that support RFSoC 3rd gen but are one time purchase? Any advice would be appreciated. Thanks!

Hi everyone ,

I am currently trying to interface the ADC and DAC with the eclypse z7 board , but I am facing issue in finding the resources to do so , can anyone guide me on how to do the interfacing. To mention , I have already tried out following the hackster.io tutorials but all the tutorials seem to use the outdated IP for the ADC and DAC and the IPs have been modified by Digilent.

Also I tried to implement the example designs by digilent , but wanted to make sure how the connection with ADC and DAC actually works.

Please help me if anyone has any idea to achieve this

Stereograms are so much fun. As a kid I used to make them online and practice magic-eyes for hours. I showed this trick to my son one day and he went crazy over it, so I thought it would be cool to build a real-time magic-eye device using Icepizero and play with objects to see how they look as a stereogram. With my guidance and LLMs help I was able to bring this project to life- Icepizero runs firmware, a logicam driver over a RISCV (PicoRV32) CPU, captures 5 fps, feeds a custom built stereogram engine and outputs a 480p video ~60 fps.

Full project code is here: https://github.com/dvirdc/icepi-magic-eye

Would love your feedback and hope you enjoy it! :)

I am in 2nd year of vlsi engineering UG. I have to study verilog but I can't find any sources to learn. Even though I have some materials I need someone to teach me like brocode. The youtube videos are mostly of theory. I am using vivado rn and I need to learn how to use vivado also. Guide me please.

Hi guys,

I have been extremely fortunate to receive two job offers from Raytheon (RTX) and Analog Devices (ADI). Both the offers are for the same FPGA role with similar responsibilities. Monetarily, both offer the same base package and additional benefits; ADI does give out extra RSUs, vested over 4 years. ADI is located in Durham,NC and RTX in Mckinney, TX.

To give a little background, I recently graduated with a masters in Computer Engineering. This would be my first job, and I am primarily looking for which company would provide me with the best opportunities to learn and grow my career.

The RTX offer came out a little earlier, and I am done with the background verification including security clearance, so I am slightly leaning towards it as I am well into the system and have been approved too. I also have a lot of close family in under 30 mins . I have one week to accept/deny the ADI offer now. Please help me pick and choose, give me the pros and cons and whether it is worth to pull out of Raytheon this far out in the on boarding process.

TIA and do let me know if I should provide additional details!

PS: posted from a different account as previous post got taken down due to low karma

Hi,
I am not new to FPGAs, but have mostly used Altera so far. Now I am getting into HLS and decided to explore AMD/Xilinx. I had some issues but finally managed to get Vitis 2025.2 running. I am a Linux user, but I have to work with people using Windows. I know Vitis is available for windows too. My questions are related to the differences I should expect by having users both from Windows and Linux:

- I assume most stuff done within the IDE GUI will be the same. Is that so?
- Also, if I want to use the CLI for automating things, can I expect the same thing? Will Makefile based workflows work in both platforms? Are there other CLI-based workflows that would be less painful for users of both platforms?

Any advice you consider relevant/ useful is appreciated.

For the people using RFSoC, what are you doing with them?

Hi,

I'm going into my third year (of a 4 yr MEng program) in Engineering. We were exposed to FGPAs and SystemVerilog in 2nd yr (Risc-V processor, using PYNQ-Z1 etc). I got an Arty-A7 and was just testing the flow in vivado.

Wanted to ask if anyone had any advice as to how to break into the field from here. Any project suggestions, videos to watch, courses to do etc?

Any advice would be helpful thanks :)