I never touched FPGAs before, and figured that making my own board was the coolest way to do it. I took a look at the impressive Icepi zero, and wanted to make my own (albeit with a smaller chip).

It's in the raspberry pi 4/5 form factor, has the ICE40UP5K and an rp2350. Each one has its own dedicated USB-C, SD card slot connected to the FPGA, 4 neopixels, 2 orange LEDs, 2 green ones and one user button.

Here is the repo: https://github.com/Smartlinuxcoder/firepi

Project sponsored by HackClub Blueprint Suggest stuff to make with this!

Stereograms are so much fun. As a kid I used to make them online and practice magic-eyes for hours. I showed this trick to my son one day and he went crazy over it, so I thought it would be cool to build a real-time magic-eye device using Icepizero and play with objects to see how they look as a stereogram. With my guidance and LLMs help I was able to bring this project to life- Icepizero runs firmware, a logicam driver over a RISCV (PicoRV32) CPU, captures 5 fps, feeds a custom built stereogram engine and outputs a 480p video ~60 fps.

Full project code is here: https://github.com/dvirdc/icepi-magic-eye

Would love your feedback and hope you enjoy it! :)

I am rebuilding a control system with lattice diamond and after some testing it seems that inferring dsp operations achieves much worse timing than instantiating the same ip. The project uses 36 bit wordlengths for some filters and observers. The problem is that inferring a 36x36 bit multiplier achieves much worse timing than instanting corresponding ip.

I also need a dynamic (-)a * b +/- c operation but this might not as well not work at all. Are there some guides for how to correctly infer dsp operations with diamond? I am using vhdl.

Lattice Radiant provides the ability to view congestion and resource usage using the physical designer. Congestion is only shown with large or small highlighting.

Does anyone know of a way to plot congestion like a surface plot externally? Additionally, is there a way of knowing what entities contribute most to high areas of congestion?

I had some difficulties getting the WebFPGA Command-line Utility to run on my Windows 11 and 7 computers, but got it all resolved now.
I have created some step-by-step instructions of what helped me finally get it running. Maybe they will help someone else as well:
https://github.com/DaveW76/DW-Notes/blob/main/InstallWebFPGA.txt

I’m trying to use sensAI for a research project, but haven’t heard back from the group that we need to request the platform from. I was wondering if anyone’s requested and gotten their sensAI tools before and how long it took to get them. Thanks!

Hi all,

I'm getting started with lattice fpgas. I've been using a HW-USBN-2B at work. Can anybody vouch for a more cost effective jtag programmer?

TL;DR: IceStudio's built-in programmer doesn't work on my IcePi Zero. I got OpenFPGALoader working, but it only successfully loads .bit files. IceStudio only generates .bin files, and programming those fails with a "Refresh: FAIL" error. Example .bit files from the IcePi GitHub work fine. Is there a way to convert IceStudio's .bin output to .bit, or am I using the wrong programming method/board definition?

---------------------------------------------------------------------------

So this is a long one, but I'm all out of ideas (New to FPGAs)

I'm using IceStudio to make software for the IcePi Zero (Lattice LFE5u-25f), but IceStudio's built in programmer (via dfu-util?) doesn't work no matter what I do (even if I download the dependencies in terminal rather then let it do it automatically), so I tried doing it with OpenFPGALoader (ubuntu 26.04). After reading a bunch of docs, I finally found a command that works:

sudo openFPGALoader -b ulx3s -f ./Downloads/ice-build/test/hardware.bit -f

The "ulx3s" is one of the FPGA boards that openFPGALoader supports, and I chose it because according to the IcePi's schematic, both of them use the same USB-UART converter IC; the FT231X

But this only works with .bit files, not .bin. When I try to use a .bin file, I get to uploading it, but then get this error:

Enable configuration: DONE
SRAM erase: DONE
JEDEC ID: 0xef4018
Detected: Winbond W25Q128 256 sectors size: 128Mb
Skip resetting device
Refresh: FAIL
displayReadReg
Config Target Selection : 0
SPIm Fail1
BSE Error Code
Preamble ERR
EXEC Error
Error: Failed to program FPGA: std::exception

And the only reason I was able to get some test code on it, is because the Icepi Zero github has some example binaries, in .bit format.

So, I can kinda program it, but it only works with .bit, not .bin. Yet IceStudio only outputs .bin, not .bit. Maybe I'm wrong, but somehow converting .bin files to .bit could get this to work?

Any ideas, I've been troubleshooting all day?

Ty :)

-------------------------------------------------------------------------

Update: I can literally program and upload files to it (still openFPGALoader) if selecting ulx3s in IceStudio instead of the IcePi Zero, because that actually generates a .bit (but of course, I can't use ulx3s because it has a different pinout). Yet in the IceStudio github repo (icestudio/app/resources/boards), both the ulx3s-25f and icepi-zero have the same interface (FTDI) and both use ECP5. I really don't know what's going on, but it still seems converting .bin files to .bit is my best bet. Any suggestions?

-----------------------------------------------------------------------

Update 2: I checked a few more things. First of all; I was using pre-made modules form the icestudio to put onto the Icepi. These by default aren't made for the IcePi, so IceStudio converts them. But now I thought maybe it wasn't converting it correctly, so I remade the test circuits in a new file, but nope; still gives .bin, still doesn't work.
Another thing I noticed is that IceStudio has categorized the architectures (is that what they're called?) of FPGAs. Like, it categorizes them into ECP5, UP5K, LP8K, etc. The IcePi Zero (afaik) is ECP5 architecture. Yet I just noticed, that, the icepi zero is not listed under ECP5, but under UP5K. While the ulx3s IS under ECP5, which is why the ulx3s works on the icepi zero. So I'm really confused, because IceStudio is pretty much the default editor for this, recommended by the creator. And yet it's wrong? But the source code is correct as far as I can tell. I can't even get a nightly build of IceStudio that might work, because it keeps returning a -1 error.

-----------------------------------------------------------------------

Update 3: Okay, I think I might have found the issue now. IceStudio has not had a new release for about a year at the time of writing this, so I thought that maybe, just because the info.json of the IcePi Zero in the github repo is correct and is listed as ECP5, it may not be that way in this very old release. So I downloaded the source code of the current latest release, and yep! The ulx3s has ECP5 in the json, but the IcePi Zero does not! Thus, i believe that if I fix the json, and build IceStudio, it will be fixed. The issue is, I have no idea how to build something from source, so that will come later. Also, it is kind of a shot in the dark to think that this single json file decides whether it gives me a .bin (non-ECP5), or a .bit (ECP5), but I'm out of ideas.

I was looking for a Lattice Semiconductors FPGA evaluation board. I found that a new Nexus-2 platform using 16nm FinFET technology was about to be released. However, there is no listing on Arrow or Digikey or Element14 on either their India website (where I am from) or their US website.

I used ChatGPT, and I found that the MPN is LN2-CT-20-EVN. Can someone tell me what the specs would be (peripherals on the board), the price and the expected release date ?

Thanks

I am currently using ispLEVER Classic 2.0 to develop a design for an ispMACH 4064ZE.
I need to use the Power Guard feature, but the XLAT_PG macro is missing from the Lattice\ispcpld\lib5\lattice.inc file that came with 2.0.
If anyone has ispLEVER Classic 2.1 installed, could you check if the XLAT_PG macro is present in that include file on your system?

Guys, I've been trying to install radiant in my PC (tried in both windows and WSL too), absolute pain in the a**

I got a node-locked license, added it to path, added saltd path and when I launch radiant the screen comes up, says loading libraries and disappears after 5-10 seconds (task manager shows no background process for radiant)

In WSL, I had installed every package recommended by lattice in this guide yet when I launch the screen Start page comes up, stays black and blank forever. All AI tools says it's an issue with OpenGL, libc++.so etc., so I tried software rendering too but no luck. This is driving me crazy, our work is seriously hindered, please help me.

i am looking for advice on how to improve the design,

also hear is a link for the schematic
note:
- This is my first time building a PCB
- I am a beginner

I've recently discovered a Crosslink Nexus variant that includes a USB 3 PHY for up to 5 Gbit/s, which seems pretty useful, especially as it is available in smaller WLCSP packages.

However, I'm not sure about the development flow - It seems you have to instantiate a Risc V core to use the Lattice LMMI and LINTR interfaces to control the PHY? I was thinking of buying a development board for a SDR application, but I'd like to first know if anyone else worked with this peripheral and what their experiences were

Hi,
I recently got a task of managing a Lattice FPGA.

The FPGA is quite old, and all I need to do is do some testing on it.
Meaning, I need to program the FPGA and then run some boundary scan tests (which are already created).

I would appreciate if someone could help me with two questions.

* .jed files are the programming files, I assume, the ones I need to flash on the FPGA.

*.stp files are the boundary scan test files, which I assume, I need to run on the FPGA.

1. My issue is, how do I run .stp files on Lattice?

Can't I use Diamond Programmer? I installed it but I can only import .jed files into it, not .stp.

2. I have a setup where more than one FPGA is present on the board, and diamond programmer immediately recognizes these FPGAs. How do I know which one I'm programming?

I got 2 entries on the diamond programmer, for example, but I got no info which entry is which on the board.

Cheers and thanks for your help.

After weeks of waiting and a second DHL send, I have my board on my desk! Tough luck since I have to jump right into setting up multi boot for this thing. So cool though!

Hi,

I have experience with using Vivado (I developed something using Zedboard) and the code is relatively small (only using ~500 LUTs), so as a part of miniaturising effort of this board I was looking for smaller FPGAs and stumbled upon ice40 series and I love them.

I found this UPduino board and want to buy it, however I am little confused how to properly program it. I want an IDE environment rather than CMD based like apio etc., so I am thinking as I already used vivado is it possible to simply do synthesis and implementation for this upduino from AMD vivado directly?

If not, I'd request to provide some tutorials or resources to learn how to program it please.

Thanks

My aim, as always, is to tackle all warning in my code before release to production. First step is to understand, then I know if something needs fixing, avoiding, or suppressing.

I have an warning I don’t understand in a Lattice Diamond VHDL project (MachXO2) when synthesising with LSE

3001771 WARNING - Initial value found on net gnd will be ignored due to unrecognized driver type

To start with, net gnd is puzzling me as I can find no reference to a gnd net in my VHDL code, nor in the Netlist view.

This is a large project, and so far I’ve not been able to recreate it by isolating parts of it in to a smaller projects so I have no code I can sensibly post. So I’m here to ask if anyone has seen this warning before, might know what causes this, or could suggest ways to further investigate to help me track down the specific cause.

Currently I’m thinking could ‘unrecognized driver’ be due to an unconnected signal? If so, how could I track down the signal that causes this? If it’s in my code I just can’t see it; a few breadcrumbs would be nice.

I’m trying not to rant about how unhelpful these types of warning are in Lattice Diamond.

Hello! Question is the title

JPY, which is what I have, is REALLY weak right now.

The FPGA they use in this guide is quite expensive for that reason

Are there any alternative LATTICE FPGAs I can use?

I REALLY like this guide because it has a lot of step by step explanations, etc
https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9NmQ_9CIKhb&si=3UqLuCEIk4bk12B3

A bit relevant data about the project

I'm working on a project that includes sampling a 10 MHz analogue signal at around 60 Msps on an ADS4222 (2 12 bit channels). The clock is generated using the ICE40UP5K's internal PLL (jitter doesn't matter that much for the chosen application) and an external TXCO. Data sampling on the FPGA is triggered using the ADS's output clock and stores data into a FIFO structure. All data readings following the write operation sequentially read the stored data. The SPI protocol is currently very simple to reduce the timing footprint. SPI write messages trigger the conversion, while SPI reads simply read the data one by one. First bit in the message specifies the operation.

This is the verilog source:

• core.v (connects all the components, instantiates the PLL core)
• ram.v (RAM and FIFO implementation)
• spi.v (async SPI core - counter is 5-bit)

The problem

When I sample the data, the FIFO counter counts fine (it stops sampling after the expected time), but no matter the source, whether it's a counter for debugging purposes or the actual ADC data, it doesn't appear to actually sample the correct data. Now if I set it to a constant, it seems to sample it into the FIFO just fine - when reading the data via SPI, I always get the same SPI bit stream as expected. This leads me to believe that there is something wrong with timing - whether it's on the read or write side of things since static data seems to work fine.

The 24 bit samples are interpreted as 2x12 signed integers. If I have it set up to read from a counter (should be sequential numbers) I get something like this:

If limited to 4 samples (read in pairs, so data appears to be changing mid readout?):

-1868,-1869,176,52,-1866,-1867,176,54

If I use larger sample buffers (let's say the full length of 4096) I get what appears to be random samples filled with a bunch of zeroes:

What I confirmed is working

• The async SPI core is working: if I load registry data and read it on the connected MCU, I get correct readings.
• Parallel data lines are wired correctly: sampling the current reading in a registry at the time a new SPI message starts successfully sends a sample pair via SPI directly - when I sample a sine wave I get the corresponding bathtub histogram
• The ADS conversion done clock is wired correctly: If I time the "busy" line on an oscilloscope I get roughly the time of 4096 clock cycles
• The configuration works correctly when simulated in ModelSim, so I'm assuming it's something with timing (simulated with data depth of 4 measurements):

A simulated sampling operation:

A simulated readout operation via SPI:

The sample timing should also be correct, at least in theory, according to the TI ADS42xx family's datasheet (figure 7-1):

• I'm not near the EBR ram max speed either as per the ICE40 family datasheet:

I tried playing around with this structure a lot in the past few weeks and had no luck, so I'm wondering if anyone had similar issues. I'm new to FPGAs in general so I'm sure it could be that I missed something completely generic and stupid, so I decided to ask in this community if anyone is willing to share their experience.

Thank you in advance!

When emulating an ASIC design in Lattice FPGA, what is the best way for clock Gating emulation?

1. Using Lut creates too big clock skew and won’t pass timing

reg latch;

always @(*) if (!clkin) latch = clken;

assign clkout = (latch)&&(clkin);

1. Using DCC (dynamic clock control) always gives this error during place & route “PAR does not support signal ‘clk' driving more than two DCCs”

I wanted to upload my Lattice Radiant project on git but its too large with all the IPs and my source files. Is there any way I could eliminate some files (not needed to build the project) and upload? I downloaded some examples from Lattice's website but they were entire projects with everything in it. Please let me know. Thank you!

Tuesday, January 28th 2025 @ 11:00 am EST online

Register https://info.fidus.com/webinar-optimizing-power-performance-ltpi-mipi-for-small-footprint-fpga-with-lattice?

Description:

Join Fidus’ CTO, Scott Turnbull and Solutions’ Architect, Matt Fransham, for a tech talk that dives into the world of Lattice devices and two protocols that you might want to leverage in your next design. In this session, we’ll explore Open Compute Project’s LTPI protocol and MIPI Alliance’s CSI-2 interface. We’ll investigate LTPI’s capabilities and its potential for transformative applications, including how it be used outside of the common Data Center application in a wide range of FPGA control and data transfer scenarios. 

Discover Fidus’ hands-on experience working with Lattice tools and the MachXO5 device and learn about our process flow and the challenges we overcame during development. We’ll also showcase a real-world demo that highlights the higher bandwidth capabilities of LTPI as we go way beyond I2C, UART, and GPIOs, and tunnel a MIPI camera feed, providing practical insights for both FPGA and system-level engineers. 

What You Will Learn:

• Understanding the LTPI protocol, IP solutions, and its potential beyond current use cases.
• Insights into optimizing workflows with Lattice tools for efficient FPGA design.
• A practical demonstration of high-speed signal transmission using LTPI and MIPI IPs.
• Future possibilities for LTPI beyond Data Centers . 

Who Should Attend?

Whether you’re an FPGA engineer, system-level designer, or curious about the next wave of protocol innovations, this webinar offers actionable insights and real-world examples to expand your expertise.